{"ok":true,"trend":{"id":464185,"platform":"news","region":"global","key":"architect labs targets two-week chip design cycle with ai-driven verification","title":"Architect Labs Targets Two-week Chip Design Cycle with AI-Driven Verification","url":"https://news.google.com/rss/articles/CBMipAFBVV95cUxOMm5lZXdrbXhuZUkzdXp5cUNUbEVqVU5SYmRZR01VYlVBaE8tS3lwam9XNEtDaTVKMEVUbEhJQTZPVlpRa3FndkNYWmNKcEx5YTdKNVg5WmRGQWw1SjlsdWZiRTdjbjRVNW4tSjVqWFRSanhQWUs1ZGg0YUtrNjNMa3hhbWozTVp2WnRHLUhhckZjMXFnbTRNc3lMdTVORHREczdWWg?oc=5","first_seen":"2026-09-30T08:53:53.499070Z","last_seen":"2026-09-30T10:15:55.379642Z","last_rank":29,"peak_rank":29,"last_volume":null,"peak_volume":0,"seen_count":2,"score":0.7653125,"category_hint":"semiconductors","section":"technology","category":"semiconductors","summary":"Architect Labs says it wants to shorten chip design cycles to roughly two weeks by applying AI-driven verification to the process, which traditionally takes months. The claim, reported by EE Times Asia, positions the startup within a broader industry push to use artificial intelligence to speed up silicon development and reduce verification bottlenecks.","why":"AI-accelerated chip design is a hot topic as the industry seeks faster, cheaper ways to produce custom silicon","tone":"neutral","entities":["Architect Labs","EE Times Asia"],"summarized_at":"2026-09-30T08:55:24.129047Z","meta":{"via":"scan","lang":"en","term":"chips","source":"EE Times Asia","published":"Wed, 30 Sep 2026 08:24:06 GMT"},"nw":null,"promo":null,"kind":null,"importance":null,"hidden":false,"hide_reason":null,"judged_at":null,"title_en":"Architect Labs Aims to Cut Chip Design to Two Weeks Using AI","section_name":"Technology","category_name":"Semiconductors","timeline":[{"captured_at":"2026-09-30T08:53:53.499070Z","rank":29,"volume":null},{"captured_at":"2026-09-30T10:15:55.379642Z","rank":29,"volume":null}],"posts":[{"platform":"news","url":"https://news.google.com/rss/articles/CBMipAFBVV95cUxOMm5lZXdrbXhuZUkzdXp5cUNUbEVqVU5SYmRZR01VYlVBaE8tS3lwam9XNEtDaTVKMEVUbEhJQTZPVlpRa3FndkNYWmNKcEx5YTdKNVg5WmRGQWw1SjlsdWZiRTdjbjRVNW4tSjVqWFRSanhQWUs1ZGg0YUtrNjNMa3hhbWozTVp2WnRHLUhhckZjMXFnbTRNc3lMdTVORHREczdWWg?oc=5","author":"EE Times Asia","title":"Architect Labs Targets Two-week Chip Design Cycle with AI-Driven Verification","snippet":null,"posted_at":"2026-09-30T08:24:06Z","likes":null}],"elsewhere":[],"window":"7d"}}